A type of layer transfer process called SMART-CUT® is known to those skilled in the art. Details of the technique may be found in many published documents, and an example is the extract on pages 50 and 51 of “Silicon on Insulator Technology: Material to VLSI, second edition,” by Jean-Pierre Colinge published by “Kluwer Academic Publishers”.
Simple implantation (for example, using hydrogen) at a suitable implantation energy can be used to conduct the implanting step. Alternately, a co-implantation process (for example, using hydrogen and helium) with dosing of the implanting chemical types at a suitable implantation energy could be used. The bonding step typically takes place on the surface of the donor wafer that underwent implantation, which is bonded to a bonding layer made of dielectric material such as SiO2. Bonding techniques typically used by those skilled in the art include initial bonding by molecular adhesion. The document “Semiconductor Wafer Bonding Science and Technology” (Q Y Tong and U. Gösele, Wiley Interscience Publication, Johnson Wiley and Sons, Inc.) can be used to obtain more information.
During the detachment step, energy is at least partially provided, typically in the form of heat. Therefore, the thermal budget (the combination of the temperature and the duration of the heat treatment) needs to be considered to determine the moment when the layer to be transferred will be detached. Thus, a semiconductor on insulator structure may be formed. For example, an SOI structure (when the detached layer is made of silicon), an SiGeOI structure (when the detached layer is made of germanium silicon), a sSOI structure (when the transferred layer is made of strained silicon), or a GeOI structure (when the detached layer is made of germanium).
After detachment, it has been frequently observed that the transfer layer may have quite a rough surface, as well a lower quality crystalline structure on its surface. This is due especially to the prior implantation and detachment steps. Referring to FIG. 1, a semiconductor on insulator structure 30 is shown diagrammatically (composed of a host wafer 20, an electrically isolating layer 5 and the detached layer 1), which has such a reduced crystalline quality in its semiconductor part (that is, in the detached layer 1). The detached layer 1 has a defective zone 1A that includes existing crystalline defects and detrimental surface roughness. When hydrogen is used during the implanting step, the defective zone 1A typically has a thickness of around 150 nm. Furthermore, the implantation step may cause a reduction in the crystalline quality in the transfer layer 1 Treating the detached transfer layer 1 is therefore necessary to remove the defective zone 1A, and to thus recuperate at least part of the sound zone 1B of the transfer layer 1. For example, mechanical polishing or chemical-mechanical polishing (CMP) could be used to eliminate the surface roughness, and/or a sacrificial oxidation process could be used on the defective zone 1A.
For example, a five step method is described in the published US patent application 2004/0053477, in which a strained silicon layer is detached from a donor substrate including a SiGe buffer layer. The implanting step consists of making the implantation in the buffer layer, and the treatment step consists of removing the detached part from the buffer layer by means of surface polishing the SiGe, and then selective etching the SiGe with respect to the strained Si. Selectively etching permits the desired layer to be obtained that has a good quality surface finish, and without too high a risk of damaging it (which could be the case if only polishing were used). However, the use of chemical etching to treat the transfer layer may in certain cases lead to at least partial detachment problems of the bonding interface. In particular, a chemical etching treatment may cause de-lamination at the edge of the bonding layer, by attacking the edge where it touches a slice of the created structure. For example, a HF treatment could be used on an sSOI (strained Silicon on Insulator) structure comprising SiO2, buried under the strained Si, or a H2O2:HF:HAc treatment could be used (where HAc is the abbreviation of acetic acid) on an sSi/SiGeOI structure (strained silicon on SiGe On Insulator), where the buried SiGe and SiO2 layers are likely to be etched under the strained Si layer.
As an alternative process, in an attempt to overcome the aforementioned problem, the etching solution could be diluted considerably so that its action is easier to control. However, this does not provide a satisfactory solution to the problem because it does not totally resolve the de-lamination problem, and a diluted solution works more slowly. Moreover, chemical etching requires prior preparation of the surface to be etched, which typically means using mechanical polishing means. In fact, etching preparation is necessary to correct part of the major roughness which could subsequently lead to etching that is not sufficiently homogeneous and likely to create traversing defects or holes in the remaining layer. The successive use of polishing and chemical etching make the post-detachment finishing step (as well as the entire sampling method) long, complex and costly.